1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, in particular, to a method of forming a bit contact in a memory cell, etc., of a DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
In a semiconductor integrated circuit device, wiring is being micro-miniaturized in order to improve characteristics and yields. In a process of manufacturing a micro-miniaturized semiconductor integrated circuit device, there is a problem since if design margin for a contact hole is determined in consideration of deviation of alignment with lower layer wiring, the deign dimension (=hole diameter+design margin) of the contact hole would be oversized. Alignment deviation is caused by deficiency of alignment performance of a reduced projection stepper used in photolithography. Moreover, alignment deviation makes scaling down, which is one of various dimension requirements (scaling•factor) for a semiconductor process, difficult. As such, it is said that alignment deviation is a factor, which affects limits of the lithography technology more than the resolution limit.
Recently, a self-alignment contact (SAC) process, whereby design margin for alignment is unnecessary on a photo mask, has been mostly used.
In general, a DRAM memory cell has the structure, in which two neighboring transistors share a bit contact diffusion layer, and both sides thereof have a capacitor contact diffusion layer so as to form one cell. FIGS. 1 to 9 show processes until formation of a bit line of a cell transistor having the so-called COB (Capacitor Over Bitline) structure, in which a capacitor structure is formed on a conventional bit line. In each of the drawings, (a) is a top view, (b) is an XX cross-sectional view, (c) is an YY cross-sectional view, and (d) is a perspective projected view. The drawings were prepared by the inventor to explain the background art of the present invention and do not describe conventional technology itself.
Firstly, as illustrated in FIG. 1, a diffusion region (3) to be a source•drain is formed in a silicon substrate (1) partitioned by an isolation region (2). As to a cell transistor, polysilicon (4), tungsten (5), and silicon nitride (6) are laminated on a gate insulating film (not illustrated) and patterned by lithography and dry etching. Furthermore, after a silicon nitride film is formed and etched back, a side wall (7) is formed on the side surface of the polysilicon (4) and the tungsten (5) so that a gate (word line) is completed.
Subsequently, as illustrated in FIG. 2, an interlayer insulating film (8) is embedded between the gate patterns, and planarization by CMP (Chemical Mechanical Polishing) is performed until the silicon nitride (6) is exposed, so that a gate interlayer insulating film is completed.
Subsequently, as illustrated in FIG. 3, a resist (21) is applied and developed on the interlayer insulating film (8), so that a hole-shaped resist aperture (21a) to be an etching mask of a contact is formed. Here, as illustrated in the cross-sectional view (b), on the silicon substrate (1) surrounded with the isolation region (2), three resist apertures (21a) (total six in (a)) are arranged between the gate patterns.
As illustrated in FIG. 4, the interlayer insulating film (8) exposed from the resist aperture (21a) is etched through dry etching until the diffusion region (3) is exposed, so that an interlayer insulating film aperture (8a) is formed. Thereafter, the resist (21) is removed from the surface of the interlayer insulating film (8), so that a cell contact hole is formed.
As illustrated in FIG. 5, a conductive film (not illustrated) is formed on the interlayer insulating film (8), and an extra conductive film on the interlayer insulating film (8) is removed through CMP, so that a cell contact (11), in which a conductive film is embedded, is self-aligned.
In the subsequent process of FIG. 6, an interlayer insulating film (13) for formation of a bit contact is formed on the interlayer insulating film (8), and furthermore, a resist (22) is applied and developed thereon, so that a hole-shaped resist aperture (22a) to be an etching mask of a contact is formed. Here, as illustrated in the cross-sectional view (b), on the silicon substrate (1) surrounded by the isolation region (2), one resist aperture (22a) (total two in the word line direction in (a)) is positioned between the gate patterns.
As illustrated in FIG. 7, the interlayer insulating film (13) exposed from the resist aperture (22a) is etched through dry etching until the contact (11) is exposed, so that an interlayer insulating film aperture (13a) is formed. Thereafter, the resist (21) is removed from the surface of the interlayer insulating film (13).
In the process illustrated in FIG. 8, a conductive film (not illustrated) is formed on the interlayer insulating film (13), and an extra conductive film on the interlayer insulating film (13) is removed through CMP, so that a bit contact (15) embedded in the interlayer insulating film aperture (13a) is completed.
Finally, as illustrated in FIG. 9, a conductive film (not illustrated) is formed on the interlayer insulating film (13), and furthermore, a resist (not illustrated) is applied and developed thereon, so that an etching mask (not illustrated) for a bit line is formed. Thereafter, the conductive layer exposed in the resist aperture is etched through dry etching until the interlayer insulating film (13) is exposed, so that a bit line (16) is completed. Subsequently, the resist is removed from the surface of the interlayer insulating film (13).
In the conventional cell contact (11) and bit contact (15), a hole is formed by forming a pattern on a resist through lithography and processing it through dry etching. As such, the dimension of a completed resist pattern and the precision of dry etching significantly affect the shape of a completed contact. This influence will be described with reference to FIG. 10. Meanwhile, (b) and (d) in FIG. 10 are cross-sectional views based on the YY line of (a) and (c) in the same drawing.
After optimum dry etching, the interlayer insulating film aperture (13a) is formed in a predetermined position as illustrated in FIG. 7.
FIGS. 10(a) and (b) show a contact hole pattern in the case where an aperture contact portion (18) is formed due to overlapping of neighboring patterns, which is caused from shortage of isolation margin upon exposing a resist pattern. The shortage of isolation margin becomes significant if with micro-miniaturization, the distance between word lines is reduced, and furthermore, the distance between diffusion layers in the direction of word lines is reduced.
FIGS. 10(c) and 10(d) show a contact pattern in the case where a non-aperture (19) is partially formed during etching, as a result of local deviation of dry etching.
Although the pattern irregulars illustrated in FIG. 10 have increased with micro-miniaturization of a semiconductor device, it has poor supported by conventional technology using a hole pattern. This problem is not limited to formation of a bit contact. Even in a cell contact formed by a SAC method, although the spacing between word lines can be reduced, the same problem may occur if the distance between diffusion layers in the direction of word lines is reduced.
Japanese Patent Laid-Open No. 2001-223155 discloses a photolithography process, in which a contact aperture is set small. This document discloses a process of exposing mutually crossing line patterns on a negative resist twice and developing a non-exposed portion between the line patterns to be used as a contact aperture mask. In this case, by adjusting the spacing of the line patterns, a desired size of an aperture mask is formed. In this process, shortage of isolation margin upon exposing a resist pattern is resolved. However, like a hole pattern, partial deviation of dry etching cannot be resolved.
Japanese Patent Laid-Open No. 2000-36573 discloses a process of reducing the spacing of contact holes and forming relatively large contact holes in the case where a bit cell contact and a capacitor cell contact are close to each other due to disposition of diffusion layers. According to this process, shortage of isolation margin upon exposing a resist pattern is resolved by forming a thin hard mask layer consisting of polysilicon on an interlayer insulating film forming a contact hole, and forming every other hard mask patterns for apertures of neighboring contact holes through two times of hard mask etching. However, since the hard mask etching is performed twice, the process is complicated. Further, the problem in local deviation of dry etching still exists.
There is an over etching method to resolve local deviation of dry etching. However, since a word line to be a gate electrode is disposed below a bit contact, and an insulating film insulating between the gate electrode and the contact is etched in the portion, in which etching is performed fast due to the over etching, short circuit or other problems may occur. In particular, if a micro-miniaturized cell contact is formed by the SAC method, a contact hole aperture formed thereon is larger than the diameter of the top surface of the cell contact, so that etching of the insulating film covering a word line cannot be avoided. Thus, the over etching has a limit in resolving local deviation.
Meanwhile, Japanese Patent Laid-Open No. 2005-94044 discloses a technique of forming a cell contact by using a line pattern (slit pattern) extending in a longitudinal direction of an active region. This technique pursues additional reduction of a cell contact by additionally forming a side wall after forming a slit pattern. However, since a bit contact formed on the cell contact is manufactured by a conventional method, the problem in forming a bit contact described above is not considered.
As described above, even though conventional technology might have resolved shortage of isolation margin upon exposing a resist pattern, it has complicated processes. In addition, as long as a hole pattern is formed, local deviation of dry etching cannot be resolved. In particular, no technical solution with respect to forming a bit contact has been developed.